1. Technical Field
The present invention relates generally to computer systems, and more specifically to DMA transfers on computer systems.
2. Background Art
To improve computer system performance, direct memory access (DMA) devices are often used to transfer data between input output (I/O) devices and system memory. These devices provide for block data transfer in either direction. Typically, all that is required for a DMA transfer is control of the bus, a starting address, and a length of block count.
The standard DMA interface between memory and an I/O port works well when there is a direct, dedicated connection between the DMA controller and the I/O device. However, in some systems, such tight coupling between the DMA controller and the I/O devices is not possible. For example, in the System2 bus used in the IBM PS/2 series of microcomputers, also known as the microchannel bus, such close coupling between the I/O devices and the DMA controller connected to system memory is not possible. In these machines, there are actually two buses. A first bus, referred to as a system bus, connects the central processor, system main memory, and an I/O cache controller (IOCC) which includes the functions of a DMA device. Also attached to the IOCC is an I/O bus. It is this I/O bus which is referred to as the microchannel bus.
I/O devices which are to be attached to the system communicate through the I/O bus. They communicate only indirectly with the central processor and system memory through the IOCC. The IOCC then passes data transfers on to the central processor and system memory.
Since two separate buses are involved, the standard DMA configuration cannot be used. All of the I/O devices on the I/O bus reside in an I/O address space, and must be separately addressed by the IOCC. This means that the IOCC must generate an address to read an item of data from an I/O device, read that data item from the bus, generate an address on the system bus, and place the data item on the bus. This results in a system where the interface between the two separate buses, the IOCC, must read from one bus on one cycle and write to the other bus on the next cycle. This results in a certain amount of system inefficency since both buses are only operating at half capacity.
It would therefore be desirable to provide an interface between two buses which could improve DMA data transfer between an I/O device on one bus and a system memory on the other bus.